Digital Equipment Corp yesterday assembled some 100 journalists at its $200m production facility in South Queensferry, Scotland, to talk about its forthcoming 64-bit Alpha RISC chip. The first product, the RISC 21064 is said to be sampling now and is due to ship in volume by the middle of the year, costing $3,375 in orders […]
Digital Equipment Corp yesterday assembled some 100 journalists at its $200m production facility in South Queensferry, Scotland, to talk about its forthcoming 64-bit Alpha RISC chip. The first product, the RISC 21064 is said to be sampling now and is due to ship in volume by the middle of the year, costing $3,375 in orders of up to 100 units, $1,650 for between 100 and 1,000, and $1,560 for volumes of over 1,000. The new RISC will be licensed to computer vendors, as it has been to Cray Research Inc and, as reported (CI No 1,866). Kubota Co Ltd has licensed the chip, pledging to deliver a high-performance graphics workstation based on the chip by the year end; the design of the chip and Alpha software will also be made available under licence, and DEC says it will offer Alpha products at the chip, board and system level under its new Open Business Practice. Pier Carlo Falotti, president and chief executive of DEC Europe told the meeting that some $50m has been invested in getting the Scottish plant ready for Alpha production – the whole Alpha programme has cost a daunting $1,000m so far – and that 450 new jobs have been created. He promised that DEC would not desert its MIPStations or VAX products in favour of the scalable RISC, which is claimed to deliver 400 MIPS peak. The 21064 part – 64-bit RISC for the 21st Century presumably – is described as a 0.75 micron CMOS superscalar, superpipelined device with 150MHz clock, using dual instruction issue, and already has multiprocessor support built in: the Privileged Architecture Library Code supports optimisation for multiple operating systems, flexible memory management implementations and multi-instruction atomic sequences; the part has an on-chip write buffer with four 32-byte entries and on-chip pipelined floating point unit; there are 8Kb instruction and 8Kb data caches on-chip and external cache support; the data bus can be switched to 64 or 128 bits and clocked at 18.75MHz to 75MHz. The Alpha architecture features 64-bit virtual address space (Terabytes are small change to this baby); 32 64-bit integer registers and 32 64-bit floating point registers. Alpha instructions are all 32 bits long with four different instruction formats specifying zero, one, two or three 5-bit register fields. The 21064 comprises four independent functional units – – integer execution unit, floating point unit, load-store or address unit and branch unit. The integer pipeline is seven-stage, the floating point is 10-stage. The physical address space of the 21064 is 16Gb.Kubota Co Ltd, Osaka says that its Kubota Pacific Computer Inc in Santa Clara and Kubota Computer in Tokyo will use the Alpha in the next generation of its Titan multi-processor graphics supercomputers, inherited from defunct Stardent Computer Inc, saying that it plans to augment its current Titan product line to include a full range of products using Alpha chip, from desktop units to data centre systems, all designed for three-dimensional graphics and imaging applications, maintaining binary compatibility with all applications developed for DEC’s implementation of OSF/1. Development of Kubota’s new Alpha-based Titan has already begun. Kubota also emphasised that it intends to continue enhancing its current MIPS Computer Systems Inc R-series-based Titan line and will have a new new graphics subsystem for both the R and Alpha RISC models.