ARM has introduced its new advanced system intellectual property (IP), CoreLink CCN-504 cache coherent network, which claimedto deliver up to one terabit of usable system bandwidth per second.
With the new application, SoC designers can provide high-performance, cache coherent interconnect for 'many-core' enterprise applications built using the ARM Cortex-A15 MPCore processor and next-generation 64-bit processors.
The company has also unveiled the new ARM CoreLink DMC-520 dynamic memory controller, which is designed to work with the CoreLink CCN-504, provides a high-bandwidth interface to shared off-chip memory, such as DDR3, DDR3L and DDR4 DRAM.
CoreLink CCN-504 enables a coherent, high-performance many-core application that supports up to 16 cores on the same silicon die.
It also enables system coherency in heterogeneous multicore and multi-cluster CPU/GPU systems by enabling each processor in the system to access the other processor caches.
The CoreLink CCN-504 claimed to support both the current-generation high-end Cortex-A15 processor and future ARMv8 processors and is built on AMBA 4 ACE specification.
ARM Processor Division deputy general manager Tom Cronk said CoreLink CCN-504 and DMC-520 provides high-performance system IP applications for many-core applications.
"This ensures quality of service and coherent operation across the system, and enables SoC designers to efficiently prioritize and handle wide data flows with optimum latency," Cronk said.
The CoreLink CCN-504 cache coherent network includes integrated level 3 (L3) cache and snoop filter functions.