Those that read the first part of this dissertation (CI No 2,4XX) may be wondering where chapter 3 went. We skipped it in our haste to jump into the delights of abstraction. But as it happens, that chapter, headed Architecture Guidance is intimately connected with the sixth section in the tome the reference implementation. They […]
Those that read the first part of this dissertation (CI No 2,4XX) may be wondering where chapter 3 went. We skipped it in our haste to jump into the delights of abstraction. But as it happens, that chapter, headed Architecture Guidance is intimately connected with the sixth section in the tome the reference implementation. They are, by far, the longest two sections in the work. The former sets out the theoretical architecture that PReP-compliant machines should follow bi-endian operation, bus structure, the memory map and multiprocessor considerations are all there. The reference implementation puts the architecture into practice and presents a complete blueprint for a generic PowerPC-based machine. It is generally accepted that at least one of IBM Corp’s Power Personal’s forthcoming machines will bear a striking resemblance to this implementation. The PReP architecture defines a hierarchy of buses.
At the top is the 64-bit PowerPC bus used for shuttling data between processors, cache and system memory. This primary bus is connected via a bridge to a secondary bus supporting all of the other input-output devices. If necessary a slower, tertiary bus can also be implemented, bridged onto the secondary one. The reference implementation shows the architecture to the fullest. The secondary bus is a 32-bit Peripheral Component Interconnect affair, which has the video display system (with integral video RAM) and a SCSI-2 port attached. A 16-bit AT bus hosts audio, and floppy drives. Both have spare slots available. Rather than attempting a definitive description of the architecture and reference system – you can get your own copy if you want that it’s worth highlighting some of the more noteworthy parts. For example, although there is no reference to upgradability in the PReP architecture, the reference machine includes a 200-pin upgrade slot attached to the processor bus. This can be filled with either an L2 cache board or a processor upgrade board. Unfortunately, the beta version of the document makes it explicit that this slot cannot be used for multiprocessing, so while you will be able to shove a shiny new PowerPC 604 processor into the machine, the old 601 will then be disabled. Although you can’t achieve multiprocessing through this slot, symmetric multiprocessing is covered in some detail in the beta version of PReP. A new section in chapter 3 gives a detailed scheme for arranging interrupts in an symmetric multiprocessing PowerPC-based system, and appendix A gives a potential two-way implementation for developers to ponder. Basically it boils down to more level-2 cache, multiple PCI buses and more system memory. There also need to be additional facilities for handling interrupts and interprocessor communication. The 601 and 604 processors provide a number of commands for keeping processors synchronised. These are missing from the 603. Endianess is another subject that crops up repeatedly in the Reference Platform specification. Its etymology dates back to 1726, when Jonathan Swift wrote Gulliver’s Travels and of a people warring over the most appropriate end to crack a boiled egg. Swift fell upon the feud between the ‘Big-Endians’ and the ‘Little-Endians’ as the crassest, most pointless argument he could invent, and it is appropriate that its name lives on to describe an arbitrary schism that has divided the processor world for its entire history. A Big-Endian processor is one that stores applications and data in the format big end first, most significant bit first. A Little-Endian processor stores it little end first, least significant bit first. Imagine a world where some people wrote English like this and others wrote siht ekil and you have more or less got it. Endianess is arbitrary, as far as anyone can argue, one is not better than the other, however, over the years, some manufacturers have adopted Big-Endian methods (IBM’s Power, Motorola’s 68000 family), others have opted for little Endian, notably Intel Corp and Digital Equipment Corp. It is not easy to isolate the operating system fr
om the Endianess of a processor, so, in keeping with their heritage, AIX and Macintosh System are Big-Endian, Windows NT and OS/2 for the PowerPC (nee Workplace OS) are Little-Endian. So how do you support all of these on one computer system? You make it Bi-Endian.
By Chris Rose
Natively, the PowerPC is a Big-Endian chip, however at the flick of a bit it can swap its proclivities. PReP-compliant machines must be able to run in either mode. Apple Computer Inc nearly managed to make its hardware Bi-Endian, but apparently fluffed it – a very few components in the Power Macintoshes work only in a Big-Endian manner, however Apple intends to fix this in future machines – a step on the long road to PReP compliance. Being Bi-Endian does not require that the system can simultaneously support Big and Little-Endian software. The processor’s Endianosity is set at boot time, and a system reset is required to change this. Theoretically, it is possible to build a machine that, through emulation and translation software could run both at once, this would be a so-called Mixed-Endian machine. Unfortunately the cost in processing terms would be ruinously high. The Endian question has more than a theoretical bearing, it means that building a Apple System 7 personality to sit on top of Workplace OS is a tough task. Likewise producing an AIX personality will be no mean feat. Which brings us neatly to the appendices, with their descriptions of the various operating systems. By far the most revealing is the section on AIX. It is from here that the rumours of Personal AIX spread – a pre-amble talks about The AIX 4.1 Personal Productivity Client (shortened later to Personal AIX) and explains that it represents a major improvement to the terms and condition and packaging for AIX (translation – you will be able to get single user licences cheap). It is being aimed at engineers and researchers that want an entry-level workstation-cum-personal computer and will come pre-installed. Pay particular attention, as you flick through, to the section on the AIX Hardware Abstraction Layer. Today AIX doesn’t have one – not a microkernel, or a thin layer of isolating code in sight. The section on AIX’s Hardware Abstraction Layer begins IBM makes no claim that this [the HAL] will ever be implemented or that the abstraction will ever enable a shrinkwrapped AIX or enable a third party to provide components of the abstraction. In other words, AIX may continue to break all the rules.
To confuse things slightly, the AIX team in its initial design investigation talks about a Portability Assist Layer, rather than a Hardware Abstraction Layer, but the outlined approach looks identical. There is, of course, absolutely no reason why IBM should re-architect AIX: it was designed for the Power/PowerPC architecture and is perfectly happy running on the naked hardware. Still, it does reveal a certain chutzpa, when the rest of the document is dedicated to trumpeting the importance of compliance. It also means that the first PowerOpen implementations (based on AIX) will not be able to carry PReP-compliant stickers. By contrast, both Windows NT and Workplace OS are well behaved, though there is not much new to be gleaned. The Windows NT Hardware Abstraction Layer looks like a good match for PReP’s Run-Time Abstraction Layer. There is still a big hole, however where the section on Boot Time Abstraction Requirements is meant to be, so there are no details on the operating system loader that NT expects to use at Boot Time. Likewise, Workplace OS’s microkernel structure serves to bundle all of the hardware specific code into one, small, -well-defined place. Not a very large book, then, to define an entire computer architecture, but still substantially larger than the non-existent tome that today’s personal computer industry is based upon. As the Reference Platform points out, when defining the AT bus, the simplest definition is Whatever it takes to make the most adaptors pluggable. Final judgement will depend on the contents of the final version, due
out later this year, and ultimately on the number of companies that decide to follow its edicts and get awarded the sticker of compliance. Exactly what will be written on the sticker is still a matter for debate. Pending market analysis A hardware platform will be branded as ‘PowerPC Reference Platform Compliant’ (or something of a similar nature), say the document’s authors, rather sheepishly. Time to wheel out the marketeers methinks. Chris Rose edits the Internet publication PowerPC News, from which this dissertation is taken.