28-nanometer multiple successful tapeouts are achieved
ASIC design, custom IP and IC manufacturing services company eSilicon has deployed Synopsys’ custom IC design offering to streamline its custom memory intellectual property (IP) business.
Synopsys’ comprehensive unified custom implementation solution enabled eSilicon to rapidly deploy the offering and achieve multiple successful 28-nanometer (nm) tapeouts.
Custom memory IP developed by eSilicon uses complex, state-of-the-art memory architectures which include cache, content-addressable memory (CAM), SRAM, ROM, and multi-port register file (MPRF) IP.
eSilicon has adopted the complete Synopsys custom offering, including the Galaxy Custom Designer schematic and layout editor, HSPICE and CustomSim circuit simulators, IC Validator design rule checking and layout versus schematic (DRC/LVS) offering, StarRC extraction tool, and PrimeYield foundry-qualified manufacturing compliance tool for final physical signoff.
eSilicon Marketing and Business Development vice-president and IP Solutions general manager Patrick Soheili said to support eSilicon custom memory IP business, we needed a complete, integrated custom IC design tool suite that could be rapidly adopted and deployed.
The unified custom IC design solution from Synopsys, including Custom Designer, provides the productivity and performance our engineers need to quickly design and tape out IP at the 28-nanometer node," said Soheili.
Synopsys Product Marketing vice-president Bijan Kiani said Custom Designer continues to gain adoption because of the breadth and depth of Synopsys’ overall custom offering.
"The availability of iPDKs at advanced process nodes, combined with the productivity of our unified custom solution, allows designers to choose Synopsys’ custom implementation solution to achieve higher productivity in an open, standards-based environment," said Kiani.