To leverage next generation, 8 core, 12-wide issue architecture
US based semiconductor firm Intel has unveiled new architecture features of its upcoming Itanium processor, codenamed Poulson, which has eight cores and 3.1 billion transistors.
The new features include Intel Instruction Replay Technology, Intel Hyper-Threading Technology improvements and Itanium New Instructions.
The Intel Instruction Replay Technology allows the processor to utilise a new pipeline architecture to expand error detection in order to capture transient errors in execution.
The Hyper-Threading Technology supports performance enhancement with Dual Domain Multithreading support, which enables independent front and backend pipeline execution to improve multi-thread efficiency, claims the company.
Poulson is adding new instructions in four key areas, which include new Integer operations (mpy4, mpyshl4, clz), expanded Data Access Hints (mov dahr), Expanded Software Prefetch (ifetch.count) and Thread Control (hint@priority).
The new features are expected to take full advantage of the next generation, 8 core, 12-wide issue architecture by enabling the maximum amount of parallel execution.
Intel said Poulson is expected to be launch in 2012.