Intel Corp and Hewlett-Packard Co have defined their so-called post-RISC architecture as EPIC, for Explicit Parallelism Instruction Computing, a term they’re obviously not going to let the industry forget in a hurry. In EPIC more pre-processing functions are passed to the compiler, enabling EPIC-based instruction sets such as IA-64 the two have created to incorporate […]
Intel Corp and Hewlett-Packard Co have defined their so-called post-RISC architecture as EPIC, for Explicit Parallelism Instruction Computing, a term they’re obviously not going to let the industry forget in a hurry. In EPIC more pre-processing functions are passed to the compiler, enabling EPIC-based instruction sets such as IA-64 the two have created to incorporate techniques for processing larger chunks of program code more quickly. Intel claims Merced, the first chip-level implementation of IA-64 – which will also run HP Precision Architecture RISC instructions – will provide the highest processing performance available in the industry when it hits the streets in 1999 built in an 0.18 micron design and targeted at workstations and servers. Intel says a second-generation part due in 2001 will perform twice as fast, but declined to provide any measurements apart from a chart in which an 80 SPECint95 mark lay mid-way between Merced and the second generation IA-64 design. EPIC compilers will direct three instructions into 128-bit ‘wide’ packages together with information about how the instructions are dependent on each other. The compiler uses techniques new to Intel – though known by the industry – called predication and speculation to expose this explicit parallelism in the code and make available directly to the processor. When the compiler determines that operations can be performed in parallel they are sent directly to the CPU in machine code, enabling its transistors to be used more efficiently. In doing so Intel and HP say they have been able to reduce by up to 50% the need for dynamic technologies such as those found in today’s RISC and CISC CPUs such a branch prediction which they say slows performance down. The two say that because of its superscalar design, the EPIC architecture can grow to fit wider word instruction sets as they are developed. Intel says predication and speculation are just two of the techniques Merced will employ that it decided to make public.
Although these techniques are new to Intel, HP says it had been investigating superscalar, wide word and VLIW very long instruction word processing techniques for a new generation of its PA-RISC for some time before its 1994 tie-up with Intel. It had called them SUPA, Super-parallel PA internally, but at that time decided it was too big a risk to the company’s future to bet on the longevity of PA-RISC given the nature of the microprocessor industry. It was unwilling to invest the kind of money new SUPA production lines would cost and reasoned that heading for the Intel architecture would prove the most attractive exit strategy for its ISVs. HP shed little light on the core electronics and compilers it will offer with Merced to support PA-RISC customers’ applications, saying they will be the subject of a future announcement. Meantime, Intel says it is committed to improving the performance of IA-32 processors by 50% each year for several years to come. Its next IA-32 part, Deschutes, applies Pentium II technologies to an 0.25 micron design process.