Intel describes the supercomputing punch packed by new 80860XP RISC microprocessor Intel Corp’s new 80860XP 64-bit supercomputing microprocessor, announced last week (CI No 1,689), is the first device produced using the company’s proprietary 0.8-micron CHMOS V process technology. Despite new features, Mike Bond, Intel’s microprocessor applications specialist, says the 80860 XP and the 80860 XR […]
Intel describes the supercomputing punch packed by new 80860XP RISC microprocessor
Intel Corp’s new 80860XP 64-bit supercomputing microprocessor, announced last week (CI No 1,689), is the first device produced using the company’s proprietary 0.8-micron CHMOS V process technology. Despite new features, Mike Bond, Intel’s microprocessor applications specialist, says the 80860 XP and the 80860 XR are fully compatible, and software needs no adaptation to run on the new processor – to test this, Intel has been plugging the XP into various 80860 XR-based systems, on which the first silicon versions ran Unix System V.4 without any tweaks. The 80860 XP single-chip processor, which is packaged in a 262-pin ceramic pin grid array, includes a RISC integer unit, two pipelined floating-point units, a graphics unit, a 16Kb instruction unit, a 16Kb data cache, and a memory management unit. And, an on-chip bus unit supports pipelined burst transfers for an external bus bandwidth of 400Mbps. New features also include on-board support for multi-processing, parallel processing – three operations per clock – and visualisation, and on-chip hardware multi-processing support is provided – bus snooping hardware and a cache consistency protocol combine to maintain cache conherency between multiple 80860 XP processors. The device is intended to address multiple system configurations, from massively parallel supercomputer architectures to powerful desktop systems. Intel claims that at 50MHz, the 80860 XP offers 20 double-precision Linpack MFLOPS, against the XR at 33MHz which turned out 8.7 MFLOPS – while 50% of this performance increase is attributed to the different clock rate, Intel says 30% is due to the increased cache, and 10% to the burst bus. Also introduced in the 80860 XP product family are the 82495XP cache controller and 82490XP cache RAM, and a multi-processing interrupt controller. Additional offerings will include uni-processor and multi-processor versions of Unix System V for 80860 XP-based systems, as well as hardware and software development tools.
The cache controller and cache RAM building blocks together reduce bus use to 10% of the total system bus bandwidth, enabling a single system bus to share up to eight 80860 XP processors. The cache controller maintains primary and secondary cache conherency in a shared bus XP system and can be configured for a 64-bit or 128-bit system bus. It will support second level cache sizes up to 512Kb or 16 cache data RAM devices. The 82490XP cache data RAM is a 32Kb device that integrates a write-back buffer and a snoop buffer. Unix System V.4 is available now for the first generation 80860 XR microprocessor, and will be available for the new XP processor later this year. As well, a multi-processor version of Unix System V.4 – MP Unix – is being developed by an Intel customer work group, which will enable multi-processor systems to boost the number of operations per clock, as well as speeding up time to market. An early version will be available in the fourth quarter. A Unix-based development system, the 80860 Station, is out now – this includes an assembler, linker, debugger, and compilers for 80860-based system design. In the UK, samples of the 80860 microprocessor 40MHz version – costing UKP376 in 1,000-up quantities, and the 50MHz version, priced at UKP460, are out now production delayed until the fourth quarter; the device will be available with a 60MHz clock rate next year. The 82495XP cache controller, costing UKP115 each in 1,000-quantity lots, and 82490XP cache RAM, priced at UKP26, are also sampling now, to be available in volume in the fourth quarter. The multi-processing interrupt controller and concurrency control unit will sample in the fourth quarter, available in the first half next year. Also announced was a new lower speed version of the first generation 80860 XR – running at 25MHz – costing around UKP100 each in 1,000up quantities and out now.
as it shows off the networking products it acquired from LANSystems
Having acquired Provo, Utah-based LANSy
stems Inc’s Network Products Division last month (CI No 1,668), Intel Corp finds itself in possession of a set of nine new network enhancement software products which it has been showing off to the press. The acquired products are LANSpool, LANSpace, LANShell, LANSight, LANSelect, LANSchool, and ReferencePoint. The LANSpool print server, which requires 2.5Kb memory, comes in four versions – LANSpool 2.0 for Novell Inc NetWare 286 networks and LANSpool 2.0 for 80386 networks, costing UKP425 for a single-server unlimited user licence; LANSpool LM for 3Com Corp 3