Japanese researchers at Tohoku University are touting improvements in chip fabrication techniques they say could reduce the cost of semiconductor fabrication to one tenth of current costs. A variety of methods including recycling fluids and compacting machinery means rooms that currently produce 200mm silicon wafer could be used to produce 300mm parts and that the […]
Japanese researchers at Tohoku University are touting improvements in chip fabrication techniques they say could reduce the cost of semiconductor fabrication to one tenth of current costs. A variety of methods including recycling fluids and compacting machinery means rooms that currently produce 200mm silicon wafer could be used to produce 300mm parts and that the equipment needed to create 300mm wafers can be reduced to around half the size currently required for 200mm production. The manufacturing concept has been explained at several Semicon industry conferences. University researchers who spoke to EE Times say it will take at least six months to apply the concepts to real fab equipment.
