MIPS32-compatible cores execute new microMIPS instruction set architecture
MIPS Technologies has launched a new core family, which enhances system performance for cost-sensitive embedded applications such as 32-bit microcontrollers (MCUs), home entertainment, personal entertainment and home networking.
The company said that the new MIPS32 M14K and M14Kc cores are the first MIPS32-compatible cores that also execute the new microMIPS instruction set architecture (ISA), achieving enhanced performance of 1.5 DMIPS/MHz with an advanced level of code compression.
The microMIPS ISA maintains 98% of MIPS32 performance while reducing code size by 35%, translating to significant silicon cost savings,the company claims.
According to MIPS, the M14K core offers features that are optimised for MCU and real-time embedded applications, including reduced interrupt latency, flash acceleration, advanced debug features including iFlowTrace and support for AHB Lite as the interconnect interface. It is configurable and extendable, offering implementation options to minimise cost and maximise reusability.
The M14Kc core, based on the MIPS32 4KEc micro-architecture, provides Linux and Java engine and superior performance for the Android platform. It has a full cache controller and translation lookaside buffer (TLB) memory management unit (MMU), the company said.
In addition, both M14k and M14Kc cores contain new microMIPS ISA that offers 32-bit performance with 16-bit code size for most instructions. It incorporates all MIPS32 instructions and Application Specific Extensions (ASEs) including MIPS-3D ASE, DSP ASE, MT ASE and SmartMIPS ASE and new instructions for code size reduction. microMIPS ISA is backward compatible, enabling reuse of optimized MIPS micro-architecture.
MIPS is also providing complete software development tool support for the new M14K and M14Kc cores, with the Eclipse-based MIPS Navigator Integrated Component Suite (ICS) and System Navigator probes for debugging.