Intel will debut a raft of new technologies with the launch of its Montecito dual core Itanium range next year as it ramps up the platform’s reliability credentials.
Intel has already said the Montecito platform would feature multicore technology, and for starters, would have 24MB of cache, and offer DDR2 and PCI Express support.
Jason Waxman, director of enterprise multiprocessor systems, said last week that the platform would also see multi-threading come to Itanium for the first time. Intel has claimed performance boosts of around 20% from the introduction of its multithreading technology to its 32-bit product lines.
Waxman that the platform would also feature the Pellston technology which will switch off faulty cache lines, as well as the Silvervale virtualization technology, which will also appear in its Xeon range.
The vendor has previously disclosed details of the technologies without firmly pinning them down on its roadmap.
Waxman said the debut of the Silvervale technology in both its Xeon and Itanium lines meant virtualization could potentially be carried out across both platforms. Ultimately, he added, that’s an OEM decision.
Waxman also said that Montecito’s 24MB of cache would be split between the platform’s two cores.
It seems that taking this approach meant Intel could get its dual core 64 bit platform out the door quicker, and Waxman admitted that taking this approach was less problematic than a shared cache architecture. At the same time, he pointed out that the Itanium platform is not exactly short on cache in the first place, so there was less pressure to eke it out across cores.
Waxman also said that the vendor was not dogmatic on Itanium’s cache architecture, and there was no reason why split cache versions won’t appear in the future. We’ll take right approach for right processor.
Montecito will be the first Itanium built on a 90 nanometer process. Typically, the shift to smaller processes allows Intel to crank up speed, and Montecito will be no exception. The 9MB cache Madison slated for later this quarter will debut at 1.7GHz. Waxman said Montecito will have a higher frequency, though he wouldn’t say what.
Montecito will also feature a higher bus speed that the current 400MHz, though he again wouldn’t specify numbers. The Xeon is about to move to an 800Mhz bus. Waxman pointed out that Itanium’s datapath is already twice as wide as the Xeon’s.
Another advantage of the 90 nanometer shift is reduced power consumption, and Waxman said Montecito should show a 20% drop in power consumption.