Seven veils are far too few for Motorola Inc when it comes to teasing the market over its forthcoming reduced instruction set microprocessor, but the company did shed several more on Wednesday – without actually giving the part, dubbed by the industry the 78000, a name. Motorola revealed that, like the Intergraph Clipper, the processor […]
Seven veils are far too few for Motorola Inc when it comes to teasing the market over its forthcoming reduced instruction set microprocessor, but the company did shed several more on Wednesday – without actually giving the part, dubbed by the industry the 78000, a name. Motorola revealed that, like the Intergraph Clipper, the processor comes as a three chip set – CPU chip and two cache memory management units, one for instructions, one for data – and Motorola claims the family provides the highest performance available in 32-bit microprocessors. It rates it at 17 VAX MIPS and 34,000 Dhrystones and says it can generate over 50 MIPS in parallel processing designs. The part is also optimised for Unix and is source-, but not binary compatible with the 68000. Motorola claims a first for the fact that the processor chip incorporates both integer and floating point units, saying that integration of both provides a balanced architecture significant performance boost. The chip implements Harvard architecture – separate buses for instructions and data, and the memory manager caches lift the burden of doing a separate cache-memory scheme from the designer. The part has 32 32-bit registers and the processor uses a technique called scoreboarding to simplify design of compilers and applications – the scoreboard allocates the primary processor’s register set to accommodate concurrent execution and manipulation of multiple instructions, so designers can use the full register set without having to define the exact progression of data as it moves through the chip, cutting time to do optimised RISC software. The set is initially being made in 1.5 micron HCMOS, but will move to sub micron technology, and will also be implemented in super-high speed ECL. Motorola says that more than 200 companies are reviewing specifications of the processor, and early samples are being evaluated by a limited number. On the split of applications between the new family and the existing 68000 line, Motorola sees the new part being used in telecommunications artificial intelligence, graphics, three-dimensional animation, simulation, parallel processing and supercomputers, while the 68000 will remain the mainstay of the workstation business. The high performance RISC market is currently dominated by MIPS Computer, with the Advanced Micro Devices 29000 and the Sun Microsystems SPARC coming up on the rails, so Motorola is entering an already well-populated market – but availability of Unix software should get it off to a flying start. For those who are now thoroughly arous ed, Motorola will remove the rem aining veils, giving it a name, complete set of specifications, and availability in the second quarter.