Plessey Co Plc is to announce a collaborative agreement on bipolar technology with a US company next week. Plessey is looking for joint development and marketing of Emitter Coupled Logic, ECL, logic arrays, which are currently the fastest bipolar devices, and is now preparing to launch a whole family of new ECL arrays this year. […]
Plessey Co Plc is to announce a collaborative agreement on bipolar technology with a US company next week. Plessey is looking for joint development and marketing of Emitter Coupled Logic, ECL, logic arrays, which are currently the fastest bipolar devices, and is now preparing to launch a whole family of new ECL arrays this year. National Semiconductor through its Fairchild acquisition looks the likeliest candidate for joint venture, but Motorola Inc is the gran’daddy of the ECL business. Following its ?30m acquisition of Ferranti’s chip business in November 1987, Plessey is now stressing its aim to become one of the world’s top five semi-custom chip providers with the emphasis on high performance application-specific integrated circuits. It is also negotiating a second source agreement with some of the big applications specific-oriented semiconductor manufacturers in Europe and the US, for the second version of its Structured Hardware Development Environment, Shade, chip design software package, which is aimed at the CMOS market. Shade is the successor to Plessey’s Megacell design process. Silicon is now about highly standardised, highly controlled design. It is no longer about trying to make silicon for a fraction less than everyone else or about how many gate arrays you can get onto one chip. It is about the intellectual property that you can build into the design process, says head of research and development Professor Gosling, that’s why we are spending more research and development money in design. 250,000-gate ASICs Gosling underlines the importance of Plessey’s Shade process by pointing to the imminent launch by Plessey of a 250,000-gate chip, while he claims that other present day design processes are stretched to provide 50,000 gates on a chip. We decided four and a half years ago that the limitations on the potential complexities that silicon offered us had to be overcome, as well as the problem that testing time increases much faster than the gate count as chips become more complicated. We aim to get the design cost per gate down to 20 pence from our current 40 pence per gate, while the industry average is still near the ?2 per gate mark, says Gosling. Version II of Shade, as a fully self testing system, is heralded as a low design-cost-per-gate solution to the testing problem. It is now in beta test at seven sites, including one UK Ministry of Defence site, and will be in production at Swindon by spring 1989. The penalty the company pays for the process is that the resulting chips are around 20% larger than those of competitors, and this slows performance by around 5%. Plessey claims to be getting military contracts now with a requirement for this self testing process written into them. There will come a stage when it will be impossible to sell non-self-testing critical chips into the military field. The back end of the Shade compiler converts intermediate statements into a mask, called Techmapper, which makes the system technology independent. Plessey is now working to merge its Megacell and Shade processes as well as Ferranti’s Collected Diffusion Isolation, CDI, process, which was designed by AT&T Bell Laboratories. One benefit the Ferranti system brings to Plessey is that it can put both analogue and digital circuit elements onto the same chip.