The good news about Mountain View, California-based Rambus Inc’s new memory-to-processor bus technology is that it promises to speed the operation of computers using it up to 10-fold, with particular benefits in graphics applications, doing away with a whole load of clutter like caches and cache controllers and video RAMs in the process (CI No […]
The good news about Mountain View, California-based Rambus Inc’s new memory-to-processor bus technology is that it promises to speed the operation of computers using it up to 10-fold, with particular benefits in graphics applications, doing away with a whole load of clutter like caches and cache controllers and video RAMs in the process (CI No 1,878). The bad news is that every memory chip, every processor, every controller, will have to be redesigned to use it. But how does it work? Microbytes Daily has the first lowdown on the idea. The problem Rambus addresses is that data transfer rate of memory chips lags way behind a processor’s ability to handle data – each succeeding generation comes out with a best effort of 55nS access time, typically the range is 65nS to 80nS. As display resolutions increase and users demand true colour, costs are driven up because of the memory needed to supply pixels at a high rate for a flicker-free display. Animation, graphics and video also require high data transfer rates to display images in real time, and so far, the problem has been met by increasingly complex architectures using specialised multi-port dynamics or video RAMs. The Rambus concept replaces all these subsystems with a combination of masters, slaves, and the narrow, high-speed bus. The bus is 9 bits wide and can transfer data at 500Mbytes-per-second by using both edges of a 250MHz clock. Masters and slaves connect to the bus via a simple 32-pin interface. Small signal swings replace conventional, noisy TTL signals and operate in a controlled-impedance transmission line environment, the company says. All dynamic RAM sense amplifiers are converted to high speed caches and using a synchronous block-oriented protocol, the slave can be mapped as a single, large contiguous address space with front-end sense amp caches. A byte of data can be read every two nanoseconds. Geoff Tate, president and chief executive of Rambus, told the news wire expects to capture over 50% of the dynamic memory market by 1997. We’ve talked to system companies who are skeptical that we can operate reliably at these speeds, Tate said. But our waveforms at 2nS per byte are a lot cleaner than 50MHz TTL. With those three Japanese licensees, Tate said customers should start seeing chips to its design implemented in systems in 1993. Tate predicts that they will give designers the ability to jump from 8-bit VGA 256-colour palettes to low-cost 24-bit true colour graphics. Today’s limited animation will be full motion by 1995, Tate predicts. He admits Software will be the bottleneck for a while, and you’re not going to do animated graphics on today’s current monochrome displays.