Gives designers the ability to create designs that are resistant to single event upsets
Synopsys has released its Synplify Pro and Synplify Premier FPGA synthesis tools, which will enable engineers to build higher reliability into their FPGA designs through a new feature that provides automated creation and preservation of error-correction logic, including safe finite-state machines (FSMs).
In addition, a new interface for the tool allows designers to track progress and analyse synthesis results hierarchically.
For ASIC prototypers, support for Synopsys DesignWare Library MacroCell IP has been added, expanding DesignWare IP support and improving compatibility with Design Compiler.
The new Synplify software will give designers the ability to create designs that are resistant to single event upsets (SEUs) by including an option for designers to automatically preserve sequential logic.
Synplify Premier software also automates implementation of 1-hot safe FSM error detection circuitry, further increasing in-field system reliability of FPGA devices.
To improve productivity in implementing large-scale designs, the new Synplify software release expands on the tools’ hierarchical design flow capability with a new GUI interface.
Additionally, the latest release of Synplify Premier software synthesises encrypted DesignWare Library MacroCell Infrastructure IP.
As a result, these encrypted RTL cores can now be read directly by Synopsys’ FPGA and ASIC implementation tools in addition to verification tools, allowing ASIC designers to seamlessly prototype their ASIC designs in FPGAs.
The newly supported DesignWare Infrastructure IP includes ARM AMBA 3 (AXI, AHB, APB) interconnect, APB advanced peripherals, APB peripherals, microcontrollers (DW8051, DW6811) and memory controller components.
Xilinx senior marketing director of design methodology marketing Tom Feist said partnering with Synopsys enables the company to deliver highly integrated design solutions to the benefit of its mutual customers.
"As Synopsys expands support for DesignWare, it enables designers prototyping SoCs to more easily integrate their key design functionality into their Xilinx devices," Feist said.
Synopsys senior director of marketing of solutions group Ed Bard said with SoC designs becoming increasingly complex and many FPGA users requiring greater field reliability, it is vital that methodologies evolve to support robust hierarchical and safety-critical design processes.
"New features in the latest releases of Synplify Pro and Synplify Premier software enable FPGA designers to more easily pinpoint design error sources throughout the design hierarchy while improving resistance to radiation effects during operation," Bard said.