Claims to enable designers to reduce simulation time
Xilinx has unveiled the IBIS-AMI models for FPGA transceivers, which it claims will enable designers to reduce simulation time from hours to minutes.
According to Xilinx, the IBIS-AMI (I/O Buffer Information Specification – Algorithmic Modeling Interface) modeling specification enables standardised, interoperable simulation of SerDes PHYs at high levels of simulation performance and accuracy needed to predict the behavior of serial links.
The company said that, using Xilinx’s IBIS-AMI models and SiSoft’s Quantum Channel Designer software, systems designers can experiment with different combinations of channel lengths, connectors, via designs and transmit / receive equalisation to determine which configurations provide adequate operating margin and which don’t.
Pre- and post-layout simulation with Quantum Channel Designer allows designers to validate designs and reduce time to market, the company said.
David Demarinis, senior director of Xilinx Serdes Technology Group, said: Our experience helping customers implement the industry’s first 100Gbps designs has taught us that HSPICE simulations of these wide datapaths can take hours to achieve a result. As a result, we are pleased to announce the public availability of the first IBIS-AMI models in the FPGA industry to allow customers 100x faster simulation times.