The new tool suite is the design and verification tool for ispPAC devices
Lattice Semiconductor has launched version 5.0 of its PAC-Designer, a new mixed signal design software tool suite, which reportedly has new device support and improved quality of results.
According to the company, the tool suite supports the new ispClock5400D family of in-system programmable ICs, which are ideal for applications that require low-cost SERDES clock references and distributing high speed differential clocks.
Lattice said that the new tool suite is the design and verification tool for its ispPAC devices. The PAC-Designer software is a complete design environment, including everything needed for design, implementation, simulation and programming of supported devices.
Lattice claims that the PAC-Designer environment makes ispClock5400D design entry and verification easy with an interactive graphical user interface schematic diagram, which provides access to all ispClock device options such as reference frequency, output buffer driver type and divider settings. Programmable analog blocks, like the FlexiClock I/Os and CleanClock PLL of the ispClock5400D device are modified to accommodate a variety of circuit board requirements.
Chris Fanning, corporate vice president and general manager of low density and mixed signal solutions at Lattice, said: Lattice’s Power Manager devices enable the integration of various supply management functions such as hot-swap, sequencing, supervision and reset generation, both at lower cost and with in-system programmability. This latest release reduces the cost of implementation further by enabling smaller devices to integrate more complex power management functions.