The word from sources within Hewlett Packard Co is that the company is getting ready to debut a 64-way version of its high-end Superdome server using the “Madison” Itanium 2 processor in the middle of next year. We also hear that the company has slipped a few weeks on its expected ship dates for the dual-core PA-8800 processors, the kickers to its current 875MHz PA-8700+ chips.
These two machines will be the cornerstone of HP’s enterprise server strategy, and are the weapons that the company will use to peddle against IBM Corp’s 32-way Power4 and Power4+ pSeries machines, Sun Microsystems’ biggest Sun Fire machines (the 36-way Sun Fire 12000 and 72-way Sun Fire 15000s), Fujitsu Siemens’ 128-way PrimePowers, and Unisys Corp’s 32-way ES7000 Intel-based machines.
The deliveries of Madison-based Superdome servers are, of course, predicated on Intel Corp getting them out the door on time, something that the company will throw all the resources it can muster to make happen. The Madison chip is expected to run at 1.3GHz (probably with 3MB of L3 cache) and at 1.5GHz with 6MB of L3 cache memory. Madison will have a whopping 374 million transistors but because it uses a 0.13 micron process, it will still have a 374 square millimeter die size, which means it can plug into slots that currently hold McKinley Itanium processors.
We have heard rumors in recent weeks that a 64-way Madison-based Superdome server might post somewhere in the range of 500,000 TPM to 550,000 TPM on the TPC-C online transaction processing benchmark test, but our HP sources say that the machine will do well over 500,000 TPM. That probably means that 600,000 TPM is the goal, which put an Itanium-based machine at the head of the pack in SMP scalability for the time on this test. Four-way and eight-way Itanium machines show excellent scalability on the TPC-C test, but big RISC/Unix boxes like HP’s own Superdomes as well as the aforementioned behemoths still own the high end until someone gets a 64-way Itanium box out the door.
While Madison is expected to be on schedule in mid-2003, our sources say that deliveries of the Mako PA-8800, HP’s first dual-core PA-RISC chip, has slipped a few weeks. HP has been telling customers that it expected to make the deliveries of the Mako chips, which should go above 1GHz in clock speed, sometime in June, July, or August of 2003, and it is now saying that they should expect to see the machines in the August, September, or October timeframe.
As we reported back in July, the dual-core PA-8800s will snap into some existing RISC/Unix machines from HP that currently support the PA-8700 and PA-8700+ processors. Specifically, sources have confirmed that the rp7410, rp8400, and Superdome servers will support the forthcoming PA-8800 chip.
Because of this support, HP’s rp7410 (an eight-way machine), rp8400 (16-way) and Superdome (64-way) customers will be able to double the number of processors in their existing machines when the PA-8800 debuts. And because the PA-8800 is expected to have a clock speed in excess of 1GHz, compared to the 875MHz PA-8700+ processors that were announced for the Superdome servers in June 2002, customers should be able to more than double the amount of work these machines can do without changing the underlying chassis.
The Mako chip includes two complete PA-8700 cores, their integrated L1 caches, an integrated L2 cache controller on a single chip and an off chip set of L2 cache SRAMs that are packaged in a single module. Each PA-8700 core on the PA-8800 chip has a 750KB data cache and a 750KB instruction cache, yielding a total of 1.5MB of L1 cache. With the PA-8800s, HP seems to be breaking the data and instruction caches for each core and also shrinking them somewhat.
All told, the PA-8800 will have 3MB of L1 cache, which is still a lot of memory space for a processor. The PA-8800 will also have 32MB of L2 cache, which is being supplied by Enhanced Memory Systems, which is comprised of four SRAM chips that have 10GB/sec of bandwidth. The PA-8800 processor also includes an on-chip bus interface, similar to that in the IBM Power4 chip. The PA-8800 has a 128-bit, double-pumped 200MHz bus interface. This chip will, at 300 million transistors, be the biggest one created by any vendor to date, thanks to those large L1 caches.
It’s hard to say where a 128-way Superdome using 1GHz or faster PA-8800s might be on the TPC-C scale. A 64-way machine using the 875MHz PA-8700+ chips hit 423,414 TPM this past summer. If HP can get the memory and I/O balanced on the 128-way Mako machines and get HP-UX to make use of this iron properly, it is conceivable that the machines could hit 700,000 TPM to 900,000 TPM. IBM won’t have a machine in this power class until it ships the Power5-based Armada servers, its first 64-way machines, sometime in the early part of 2004. HP really wants to get the PA-8800s out the door as soon as it can so it can show better benchmarks than IBM can in late 2003.