PowerShrink reduces IC power consumption by half, claims company
Semiconductor start-up SuVolta has introduced its PowerShrink low-power platform, which the company claims reduces the power consumption of CMOS ICs, used in mobile devices, by 50% or more while maintaining performance and improving yields.
SuVolta and Fujitsu Semiconductor Limited also jointly announced that Fujitsu has licensed SuVolta’s PowerShrink low-power technology.
The company says that its new platform reduces power consumption by minimising electrical variation of the threshold voltage of a chip’s transistors. The team behind the new platform achieved this by using "Deeply Depleted Channel" (DDC) CMOS technology.
SuVolta claims supply voltage reductions of over 30% and reduction of leakage power consumption by at least 80%.
Cypress Semiconductor founder and CEO Dr T J Rodgers said SuVolta has developed an innovative way to significantly reduce CMOS transistor active and leakage power.
Rodgers added, "By tightening threshold voltage variability while maintaining performance at lower supply voltage, SuVolta’s platform extends the useful life of bulk planar CMOS processes and the products they enable and negates the need for costly, complex technologies like EUV lithography, FD-SOI or FinFETs.
Furthermore, the technology enables companies to preserve and extend the legacy IP blocks they have spent years developing."
SuVolta said that it has demonstrated large SRAM blocks operating below 0.5 volts, which is among the lowest reported for 65nm CMOS technology, and is significantly lower than typical SRAM minimum operating voltages of 0.8 volts and higher in conventional CMOS technologies.
SuVolta CTO Dr. Scott Thompson said, "Up to this point in time, semiconductor process technology innovation has primarily focused on increasing performance. But the biggest problem in semiconductors today is not performance but power."
"SuVolta is solving the power impasse by significantly reducing transistor threshold voltage variation and therefore enabling supply voltage scaling.
"SuVolta’s DDC sub-micron technology addresses threshold voltage control by limiting random and other sources of dopant fluctuation while simultaneously improving carrier mobility and reducing device capacitance so as to maintain circuit speed at much lower power."
The company said the new platform is compatible with current manufacturing and design infrastructure.
SuVolta’s DDC transistor leverages existing CMOS design rules and process flows, and can be manufactured in existing fabs because it does not require new equipment or new materials.